Keep-Out-Zone analysis for three-dimensional ICs

Said, M.; Madipour, Farhad; El-Sayed, Mohamed

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Date
2014-04
Citation:
Said, M., Mehdipour, F., & El-Sayed, M. (2014, April). Keep-Out-Zone Analysis for Three-Dimensional ICs. IEEE Xplore (Ed.), VLSI Design, Automation and Test (VLSI-TSA) International Symposium (pp.1-4). 10.1109/VLSI-DAT.2014.6834862.
Permanent link to Research Bank record:
https://hdl.handle.net/10652/3816
Abstract
One of main challenges of 3D-integration is the area overhead which has two main causes: first the huge TSV diameter which is usually in the range of microns, and the second reason is the Keep-Out-Zone (KOZ) overhead due to the high induced thermal stresses during fabrication. The area overhead besides the fabrication process itself inversely affects the overall yield and fabrication cost, so the increase in area will reduce the yield and increase the fabrication cost. In this paper, the effect of KOZ overhead on the overall area, yield, and fabrication cost is investigated. Also various parameters that might change KOZ overhead are examined. We show that the share of area overhead caused by KOZ is considerably higher compared to that of TSVs. Further, the impact of KOZ is considered for obtaining more accurate estimation on W2W overall yield and fabrication cost of a 3D-IC.
Keywords:
Through-Silicon Vias (TSVs), fabrication, multiplexing, silicon, three-dimensional displays, stress, thermal stresses
ANZSRC Field of Research:
090604 Microelectronics and Integrated Circuits
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[Blind-review copy]
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