A Highly Parallel SAD Architecture for Motion Estimation in HEVC Encoder
Date
2014-11Citation:
Medhat, A., Shalaby, A., Sayed, M. S., Elsabrouty, M. , Mehdipour, F. (2014, November). A Highly Parallel SAD Architecture for Motion Estimation in HEVC Encoder. IEEE Xplore (Ed.), 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (pp.280-283). 10.1109/APCCAS.2014.7032774.Permanent link to Research Bank record:
https://hdl.handle.net/10652/3813Abstract
The high computational cost of the motion estimation module in the new HEVC standard raises the need for efficient hardware architectures that can meet the real-time processing constraint. In addition, targeting HD and UHD resolutions increases the motion estimation processing cost beyond the capabilities of the currently existing architectures.
This paper presents a highly parallel sum of absolute difference (SAD) architecture for motion estimation in HEVC encoder. The proposed architecture has 64 PUs operating in parallel to calculate the SAD values of the prediction blocks. It processes block sizes from 4x4 up to 64x64. The proposed architecture has been prototyped, simulated and synthesized on Xilinx Virtix-7 XC7VX550T FPGA. At 458 MHz clock frequency, the proposed architecture processes 30 2K resolution fps with ±20 pixels search range. The prototyped architecture utilizes 7% of the LUTs and 5% of the slice registers in Xilinx Virtex-7 XC7VX550T FPGA.