• A design methodology for performance maintenance of 3D Network-on-Chip with multiplexed Through-Silicon Vias 

      Madipour, Farhad; El-Sayed, M.; Murakami, K.; Said, M. (ACM DL (Digital Library), 2015-06)
      3D integration is an emerging technology that overcomes 2D integration process limitations. The use of short Through-Silicon Vias (TSVs) introduces a significant reduction in routing area, power consumption, and delay. ...
    • Keep-Out-Zone analysis for three-dimensional ICs 

      Said, Mostafa; Madipour, Farhad; El-Sayed, Mohamed (Institute of Electrical and Electronics Engineers (IEEE), 2014-04)
      One of main challenges of 3D-integration is the area overhead which has two main causes: first the huge TSV diameter which is usually in the range of microns, and the second reason is the Keep-Out-Zone (KOZ) overhead due ...