Browsing by Author "Said, M."
Now showing items 1-3 of 3
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A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias
(Elsevier, 2016)The use of short Through-Silicon Vias (TSVs) in 3D integration Technology introduces a significant reduction in routing area, power consumption, and delay. Although, there are still several challenges in 3D integration ... -
A design methodology for performance maintenance of 3D Network-on-Chip with multiplexed Through-Silicon Vias
(ACM DL (Digital Library), 2015-06)3D integration is an emerging technology that overcomes 2D integration process limitations. The use of short Through-Silicon Vias (TSVs) introduces a significant reduction in routing area, power consumption, and delay. ... -
Keep-Out-Zone analysis for three-dimensional ICs
(Institute of Electrical and Electronics Engineers (IEEE), 2014-04)One of main challenges of 3D-integration is the area overhead which has two main causes: first the huge TSV diameter which is usually in the range of microns, and the second reason is the Keep-Out-Zone (KOZ) overhead due ...
